Bilkent University
Department of Computer Engineering
CS 590 SEMINAR
Hardware/Software Mechanisms to Enhance the Effectiveness of Directory Based Cache Coherence
Erdem Derebaşoğlu
MS Student
Computer Engineering Department
Bilkent University
Over the last decade, we have been witnessing a dramatic shift in processor design. Processors with very powerful, more complex and more power-hungry single superscalar core running at very high clock speeds have been replaced by chip multiprocessor (CMP) systems, which have multiple cores in the same chip with each less powerful, simpler, consuming less power per operation and operating at lower clock speeds. It is a key challenge to maintain cache coherence in an efficient manner in CMPs. This is especially correct for CMPs with many cores. Directory based cache coherence protocols reduce the bandwidth overhead of snoop based protocols by avoiding broadcasting, and therefore scale to larger number cores better. These protocols maintain a directory to keep track of all private caches storing memory blocks. One of the major drawbacks of traditional coherence protocols is that they do not differentiate between communicating data shared data that is updated by one core and read by another core and the rest of the data, which we call them regular? that is, each data goes through the same protocol and placed in the same cache(s). In this project, we present some software and hardware approaches to manage cache coherence more effectively in CMPs. Especially, we try to alleviate performance, area, and power consumption overheads of directory based protocols and make the directory based protocols more scalable to a growing number of cores by governing the protocol and deciding where to place data according to their type. To accomplish this, we are planning to integrate the compiler with a preprocessor stage in order to tag each data either as communicating or as regular, helping the compiler generate different versions, in later stages, of loads/stores accordingly. Loads/stores related to communicating data will be managed by the underlying coherence protocol, and the memory access instructions for the regular data will bypass the coherence protocol, reducing the side effects of the coherence protocol.
DATE: 21 March, 2016, Monday @ 15:40
PLACE: EA-409