Bilkent University
Department of Computer Engineering

---

S E M I N A R

 

A Scalable Cache Coherence Scheme for Shared Memory Chip-Multiprocessor Systems

 

Mohammad Reza Soltaniyeh

Technology scaling makes it possible to lay out many cores into one single chip. However, the challenge of efficiently managing memory system and more specifically caches, still exist. It is a key challenge to maintain cache coherence in an efficient manner in CMPs. This is especially the case for CMPs with many cores. Directory based cache coherence protocols have been employed for this reason to reduce the bandwidth overhead of snoop based protocols by avoiding broadcasting, and therefore scale to larger number cores better. However, these protocols are still struggling with some drawbacks. Two major drawbacks of these coherence protocols are power consumption and latency overhead because of high requirement of communications between cores. We try to tackle the scalability problem of directory cache coherence protocols by proposing both software and hardware mechanisms.

 

DATE: 01 December, 2014, Monday @ 16:15
PLACE: EA-409