As chip fabrication capabilities threaten to outpace design capabilities, hierarchical techniques, such as core-based designs for System-On-a-Chips (SOCs), provide hope that the gap will be bridged. The ensuing design hierarchy alters the landscape for the chip design business, providing opportunities for new companies that market predesigned intellectual property. While the design challenges may thus be partially answered, the deep embedding of the cores together with requirements for protection of intellectual property pose an even more problematic test challenge. The efficient test of SOCs hinges on the test of SOC cores in parallel; this parallelism is significantly hampered due to test bandwidth and power constraints. In this work, we propose algorithmically innovative, mathematically sophisticated, cost-effective techniques to ensure enhanced core test parallelism. Specifically, we propose test data compression and response compaction techniques that reduce the required core test bandwidth, and on-chip test data transformation-based test power reduction techniques that ensure energy-frugal test of cores. We also propose a partial core encapsulation methodology that delivers the test of SOC cores with no employment of performance-degrading test hardware. Through the test techniqes that we propose, performance-efficient, energy-frugal and rapid Test of SOCs can be realized.

DATE: March 26, 2004, Friday @ 15:40
PLACE: EA-409